The present invention relates to testing integrated circuits and more particularly to testing large scale and very large scale integrated circuits having relatively few pin connections.
The use of computer aided design/computer aided manufacturing (CAD/CAM) has had some profound effects on the world of integrated circuits. CAD/CAM has not only helped to design and develop individual circuit functions, such as counters, buffers, flip-flops, controllers, etc., but also provides the capability to store each individual circuit function as a `cell` in a library. The cells then can be assembled and connected to form large and very large scale integrated circuits for performing complex functions. Thus, CAD/CAM has made possible the production of single integrated circuits which can replace entire printed circuit boards of simple, single function integrated circuits.
Microprocessors, random access memories, and application specific integrated circuits (ASICs) are common examples of large or very large integrated circuits having complex functionality. Each of these large integrated circuits, when completed, often requires between fourteen and two-hundred eighty pins to connect it to power and signal inputs and outputs from the printed circuit board upon which it is mounted.
The problem that arises is that the approximately ten thousand or more active circuit devices of each integrated circuit can only be accessed by the fourteen to two-hundred eighty pins required for power and signal inputs and outputs after the integrated circuit has been mounted and packaged. In complex integrated circuits this often means that some embedded logic functions cannot be tested, and other embedded logic functions can only be tested in combination with one or more levels of related logic functions.
One solution has been to add internal test circuitry in order to access test locations within the integrated circuit, and to add one or more pin connections for inputting and/or outputting test signals. But, there has always been a tradeoff between the cost of additional test circuitry and additional pin connections, on the one hand, and the money saved by improved testability during the production cycle and the maintenance cycle of a complex electronic unit.
A previous approach includes additional test circuitry on each integrated circuit which allows some access to embedded test locations. To keep the overall number of pin connections to a minimum, these integrated circuits use the input/output pin connections as access points for the test inputs and test outputs. However, to maintain a separation of the test circuits from the operating circuits, this type of integrated circuit uses special gating devices which are responsive to d.c. voltage level shifts. Thus, to perform a test, this type of integrated circuit must have certain d.c. voltage levels shifted. This type of operation, while improving testability with minimal increases to the number of pin connections, makes switching between test conditions and operating conditions slow and cumbersome. Additionally, d.c. level shift testing is very difficult to perform once the integrated circuit has been mounted onto a printed circuit board because of the effect of the level shifts on attached circuitry.
One conclusion reached by the integrated circuit industry is that some increase in the size of an integrated circuit chip is cost effective when access to otherwise embedded logic levels are provided to simplify the testing. This conclusion has been reached even though an increase in circuitry automatically means fewer chips are possible per wafer and a lower yield per lot because of a statistical increase per chip in the possibility of defects. The industry thus recognizes that the costs which would be expended on test equipment and test technicians during the production and maintenance cycles to assure proper operation of a complex integrated circuit may be greatly reduced by a relatively small increase in the overall cost of including internal test circuitry to the complex integrated circuit.
A second conclusion of the integrated circuit industry is that one or more pin connections must be added to each integrated circuit in order to provide input and output access for the test circuitry. This conclusion is reached by the industry even though the number of pin connections available to connect the internal functionality with the external printed circuit board often is the greatest limitation faced by the integrated circuit designer. This second industry conclusion is demonstrated by the acceptance of one or more test pin connections as a requirement for testing of large and very large scale integrated circuits by the Joint Test Action Group (JTAG) and the proposed IEEE P1149 standard.
It is an object of the present invention to provide a method for accessing embedded test locations within an integrated circuit without requiring one or more additional test pin connections.
It is another object of the present invention to provide a method for accessing embedded test locations within an integrated circuit without requiring a d.c. level shifting of one or more pin connections.
It is another object of this invention to provide an apparatus for accessing embedded test locations within an integrated circuit without requiring one or more additional test pin connections.
It is another object of this invention to provide an apparatus for accessing embedded test locations within an integrated circuit without requiring a d.c. level shifting of one or more pin connections.